Referring to FIG. 1, to represent an integrated circuit in a way consistent with the semiconductor manufacturing technology, circuit designers convert a circuit design into a series of physical layouts that consists of simple geometrical shapes by means of computer aided design (CAD) tools (Block 101). The physical layout represents shapes that are meant to be manufactured on the wafer, for example, by photolithography, wherein the physical layout is represented as shapes on a lithographic mask, and corresponding shapes are formed on a wafer by imaging the mask shapes onto the wafer by processes, for example, such as exposing a photoactive material (e.g. a photoresist), followed by patterned etching.
Due to resolution limitations, current state-of-the art manufacturing tools (such as lithography systems) are not able to reproduce shapes on the wafer that are taken directly from the CAD tools. Thus, simple CAD shapes are processed by another software tool—the Optical Proximity Correction (OPC) tool, which modifies the mask shapes to account for such resolution limitations (Block 105). An OPC tool, having a CAD physical layout as an input, pre-distorts or modifies the shapes in such a way that a lithography system, which use the OPC pre-modified shapes as an input (e.g. as formed on a lithographic mask or reticle), produce physical shapes on a silicon wafer that are as close as possible to the original CAD shapes. An OPC tool is part of data preparation (DP) for manufacturing of a reticle (Block 110). A reticle is a physical media on which the OPC modified design shapes are materialized in the form of dark and bright areas. The reticle is a part of a lithography system that is used to form the intended physical layout on a silicon wafer.
A model-based OPC (MBOPC) tool typically distorts layout shapes by breaking the edges of the original physical layout shapes into small pieces (fragments) (Block 102). Then, associated with each fragment, simulation sites are defined (Block 103). The MBOPC algorithm (Block 105) includes the following steps. The image produced by the layout shapes is simulated at the associated simulation sites by a model, which typically includes optical processes, and may also include semiconductor processes (Block 106). The MBOPC tool then compares the simulated images at the simulation sites to the target shapes that are to be produced on the wafer, for example, by determining the edge placement error (EPE) (Block 107). The OPC algorithm then moves the associated fragments into positions to correct for deviations of the image from the target design shapes, within pre-defined tolerance criteria (Block 109), and the simulation is repeated as necessary, until the EPE is sufficiently small or other acceptance criteria are met (Block 108). Number of points where the new edge position has to be calculated (hence number of fragments) affect the MBOPC processing time (aka runtime). To have a reasonable runtime for modern integrated circuits, number of fragments and simulation sites have to be minimized but not denigrate the quality of OPC distortions.
However, the placement of simulation sites and the method of breaking the physical layout into fragments in MBOPC are determined by certain rules, for example, as defined in a user recipe template or setup file, prior to applying the model and prior to movement of edges. Such rules are based on general heuristics, and may not adequately account for local characteristics of the layout.
For example, referring to FIG. 2A, a layout shape 200 is fragmented according to fragmentation points a-h, thus defining edge segments a-b, b-c, c-d, d-e, e-f, f-g, g-h and h-a. Simulations sites are assigned to edge segments, for example, site 201 corresponding to segment b-c, site 202 corresponding to segment d-e, site 203 corresponding to segment g-f, and site 204 corresponding to segment a-h. Simulation sites are not necessarily assigned to every edge segment. However, if the fragmentation is not fine enough, the match between the simulated image 210 and the target image 200 may be excellent, within a pre-defined tolerance, at the simulation sites 201, 202, 203, 204, but may deviate significantly at non-simulation sites, as for example indicated by deviations 211 and 212. Even if addition fragmentations points, for example, i, j, and additional simulation sites, for example at 205 and 206, respectively, they may not correct the problem, as illustrated in FIG. 2B, where the additional simulation sites 205, 206 happen to be located where the agreement is good between the simulated image 210 and the target image 200, but the deviations at 211 and 212 are not significantly improved. On the other hand, placing finely spaced fragmentation points (indicated as circles or dots, such as a-h, but which, for clarity, are not all labeled), as illustrated in FIG. 2C, which have many corresponding simulation sites (indicated as lines vv intersecting the target image 200 between each fragmentation point), which may result in a simulation image 220 that is very close to the target image 200, but the large number of simulation sites results in impractical turnaround time.
In view of the above, there is a need in the semiconductor industry to provide a method of performing MBOPC, and in particular, for selecting fragmentation and simulation sites that provides improved image quality while minimizing runtimes.